RS¶
Reset-dominant bistable function block. A flip-flop where the reset input takes
priority: if both S and R1 are TRUE, the output Q1 is
FALSE.
IEC 61131-3 |
Section 2.5.2.3.1 |
Support |
Supported |
Inputs
Name |
Type |
Description |
|---|---|---|
|
|
Set input. Sets Q1 to TRUE while TRUE, unless R1 is also TRUE. |
|
|
Reset input. Clears Q1 to FALSE while TRUE; takes priority over S. |
Outputs
Name |
Type |
Description |
|---|---|---|
|
|
Latched output state. Retains its value between scans. |
Behavior¶
The output is computed as Q1 := NOT R1 AND (S OR Q1). When R1 is
TRUE, the output is cleared regardless of S. When only S is
TRUE, the output is set. The output retains its value between scans
(latching).
Example¶
This example shows that reset dominates: both S and R1 are TRUE,
yet output is FALSE.
PROGRAM main
VAR
latch : RS;
output : BOOL;
END_VAR
latch(S := TRUE, R1 := TRUE, Q1 => output);
(* output is FALSE because reset dominates *)
END_PROGRAM
See Also¶
SR — set-dominant bistable